1. Field of the Invention
The invention relates to a data processing apparatus. More particularly, the invention provides a circuit for processing signals so as to carry out an inverse discrete cosine transform (IDCT) of input data.
2. Description of Related Art
Discrete cosine transform (DCT) and IDCT are used in many types of systems for processing data. One common use is in video technology. DCT and IDCT are specified in various standards for compressing image signals because they demonstrate good energy compactness and low computational complexity. The standards, such as the CCITT H.261 standard for video telephony and teleconferencing, JPEG (Joint Photographic Experts Group) for color still image transmission, MPEG (Moving Picture Experts Group) standard for moving pictures on a storage media, and the standard for future HDTV systems, utilize the DCT/IDCT to encode and decode the image data. Therefore, a high speed DCT/IDCT processor has become a key component in image compression VLSI (Very large scale integrated) circuits.
In the past, most two-dimensional (2-D) DCT/IDCT algorithms have been implemented by using equivalent 1-D DCT/IDCT processing units for VLSI implantation. A so-called row-column decomposition, in which row data is calculated and transposed to a transposition RAM for providing transposed data to another 1-D DCT processing unit, has modular structure, thus facilitating hardware implantation. Since direct fast 2-D DCT/IDCT algorithms are too complex for implementation, there is no reference in the literature to chips that implement direct fast 2-D DCT/IDCT algorithms. However, DCT/IDCT computation using row-column decomposition is less efficient than a direct fast 2-D DCT/IDCT computation, that is, the encoding and decoding speed of the image compression VLSI can be improved by employing the direct fast 2-D DCT/IDCT algorithms instead of traditional 1-D DCT/IDCT computations.
Since there is no DCT computation in a video decoder, only the IDCT function is designed into the video decoder. Moreover, since the decoder requires a larger volume than that of an encoder and the IDCT computation is the most complicated part in the decoder, efficient 2-D IDCT computation is necessary in the video decoder. Therefore, the realization of 2-D IDCT algorithms has become the key technology in the development of high speed video decoders.
On the other hand, since row/column decomposition is a sequential operation which can not skip zero coefficients, the IDCT processing has lower efficiency. Therefore, the pixel rate of the conventional IDCT processor is generally equal or lower than a clock rate. However, since digital HDTV requires real time operation at a pixel rate of about 80-100 MHz, the prior art technology is not satisfactory. Thus, there is a great need for an IDCT processor which operates at a lower frequency but attains a very high pixel rate to meet the requirement of digital HDTV.
Furthermore, there is a need for a 2-D IDCT processor which can be fabricated in a chip by well-developed standard semiconductor fabrication techniques to reduce the manufacturing cost.